In a nominal schedule of 12 weeks and about 12 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.

This book is all an engineer needs for in-depth understanding of the verilog language: syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.